Advertisement
Continuing our coverage of AMD’s Financial Analyst Day 2022, we have the matter of AMD’s upcoming RDNA 3 GPU architecture and the Navi 3X GPUs built on top of it. Up until now, AMD has been pretty quiet about what to expect with RDNA 3, but as RDNA 2 approaches its second birthday and the first RDNA 3 products are expected to launch this year, AMD is offering some of the first key details on the GPU architecture.
First and foremost, let’s talk about performance. Planned to be built on a 5nm process (TSMCs no doubt), the Navi 3X family is targeting a performance-per-watt increase of more than 50% over RDNA 2. This is a significant and similar increase to AMD’s switch to RDNA(1) to RDNA 2. And while such a claim by AMD would have seemed demonstrative two years ago, RDNA 2 brought a significant amount of new thinking to AMD’s GPU teams given credibility.
Luckily for AMD, unlike the 1-to-2 transition, they don’t have to figure out a way to get a 50 percent increase based on architecture and DVFS tweaks alone. The 5nm process means Navi 3X gets a full node upgrade from the TSMC N7/N6-based Navi 2X family of GPUs. As a result, AMD will see a significant increase in efficiency from this alone.
That being said, nowadays a single node hop alone cannot deliver a 50% improvement in performance per watt (RIP-Dennard scaling). Therefore, several architectural improvements are planned for RDNA 3. This includes the next generation of AMD’s on-die infinity cache and what AMD calls an optimized graphics pipeline. According to the company, the GPU compute unit (CU) will also be rebuilt, although it remains to be seen to what extent.
But the biggest news of all on this front is that AMD will be using chiplets with RDNA 3, confirming rumors and several patent filings a year The GPU tier (as we know it) is moving from a monolithic GPU to a chiplet-based design style with several smaller chips.
In a way, chiplets are the holy grail of GPU design, giving GPU designers opportunities to scale GPUs beyond today’s die (reticle) size and yield limits. However, it’s also a holy grail, because the immense amount of data that needs to be transferred between different parts of a GPU (on the order of terabytes per second) is very difficult to accomplish – and very necessary when you’re running a multi-chip GPU , to be able to present itself as a single device. We’ve seen Apple approach the task by essentially bridging two M1 SoCs together, but it’s never been done with a high-performance GPU before.
Specifically, AMD calls this an “advanced” chiplet design. This moniker is often thrown around when a chip is packaged with some sort of advanced high-density interconnect like EMIB, distinguishing it from simpler designs like Zen 2/3 chiplets, which just pass their signals through the organic packaging with no advanced technologies. So while we eagerly await more details on what AMD is doing here, it wouldn’t be at all surprising to find out that AMD uses some form of Local Si Interconnect (LSI) technology (like the Elevated Fanout Bridge used for the MI200- accelerator family) to directly and tightly bridge two RNDA 3 chiplets.
At this point, AMD does not go into detail about the architecture or the Navi 3X GPUs. Today is a teaser and roadmap update for the analyst market, not an announcement of what we can only assume will be the Radeon RX 7000 family of graphics cards. With the first RDNA 3 products set to launch later this year, a more formal announcement can’t be too far off. So we look forward to hearing more about what a major shift in the nature of GPU design and manufacturing will mean.
