Zen 4 with up to 96 cores, 192 threads, 384 MB L3 cache, 400 W TDP


AMD EPYC CPUs Significantly Outperform Intel Xeon In Cloud Servers, Study Reveals

AMD EPYC 9000 “Genoa” CPU family with brand new Zen 4 core architecture was leaked Yuuki_AnS. The lineup list contains several SKUs with the correct naming, number of cores and clock speeds.

AMD EPYC 9000 Genoa CPU family leaked: 18 SKUs in the works with up to 96 Zen 4 cores, 384MB cache, 400W TDP

Starting with the details, AMD has already announced that EPYC Genoa will be compatible with the new SP5 platform, which brings a new socket, so SP3 compatibility would last until EPYC Milan. The EPYC Genoa processors would also add support for new memory and capabilities. In the latest details, it is reported that the SP5 platform will also feature a brand new socket with 6096 pins arranged in LGA (Land Grid Array) format. This will be by far the largest socket AMD has ever designed, with 2002 more pins than the existing LGA 4094 socket.

Size comparison between AMD EPYC Milan Zen 3 and EPYC Genoa Zen 4:

CPU name AMD EPYC Milan AMD EPYC Genoa
process node TSMC7nm TSMC5nm
core architecture Zen 3 Zen 4
Zen CCD die size 80mm2 72mm2
Zen IOD Die Size 416mm2 397mm2
Substrate (packaging) area open 5428mm2
socket area 4410mm2 6080mm2
socket name LGA 4094 LGA6096
Maximum socket TDP 450W 700W

The socket will support AMD’s EPYC Genoa and future generations of EPYC chips. Speaking of Genoa CPUs themselves, the chips will pack a mammoth 96 cores and 192 threads. These will be based on AMD’s brand new Zen 4 core architecture, which is expected to deliver some insane IPC uplifts while leveraging the TSMC 5nm processing node.

In order to get 96 cores, AMD has to pack more cores into its EPYC Genoa CPU package. AMD is said to achieve this by building a total of up to 12 CCDs into its Genoa chip. Each CCD has 8 cores based on the Zen 4 architecture. That aligns with the increased socket size, and we could be looking at a massive CPU interposer that’s even larger than existing EPYC CPUs. The CPU is said to have TDPs of 320W, which will be configurable up to 400W. More details on the SP5 platform can be found here.

So let’s get to the SKUs, Yuuki_AnS has leaked a total of 18 SKUs, 6 of which are still in ES state, but the rest of the 12 SKUs are production-ready. The lineup will include four “F” or frequency-optimized SKUs, three “P” single-socket SKUs, and 11 standard SKUs. Note that these are just the SKUs that have been leaked and more may be in the works. With that in mind, there will be multiple EPYC 9000 Genoa CPU configurations ranging from 16, 24, 32, 48, 64, 84 and up to 96 Zen 4 cores. Certain SKUs ship with partially enabled chiplets for increased cache, and we get up to 384MB of L3 cache. Keep in mind that “Genoa-X” V-cache variants are also planned, so we will get a total of 1152 MB LLC on these parts.

Clock speeds vary from CPU to CPU, with certain high TDP parts reaching up to 3.8GHz, while the top 96C parts run at around 2.0-2.15GHz at 320-400W TDPs. It looks like the top SKUs will feature the EPYC 9654P with 96 cores, 192 threads, 384MB cache, clock speeds up to 2.15GHz and a TDP of 360W, while a 400W variant for the dual-socket SP5 platform is also included and is listed at the same clock speeds in ES state but a higher TDP of 400W. The following is the EPYC 9000 genoa stack:

Details and specifications of the AMD EPYC 9000 “Zen 4” Genoa Server CPU family have been leaked.  (Image credit: Yuuki_AnS)
Details and specifications of the AMD EPYC 9000 “Zen 4” Genoa Server CPU family have been leaked. (Image credit: Yuuki_AnS)

“Preliminary” specifications of the AMD EPYC 9000 Genoa CPU SKUs:

CPU name cores / threads cache clock speeds TDP Federal State
EPYC 9654P 96/192 384MB 2.0-2.15GHz 360W production ready
EPYK 9534 64/128 256MB 2.3-2.4GHz 280W production ready
EPYC 9454P 48/96 256MB 2.25-2.35GHz 290W production ready
EPYK 9454 48/96 256MB 2.25-2.35GHz 290W production ready
EPYC 9354P 32/64 256MB 2.75-2.85GHz 280W production ready
EPYK 9354 32/64 256MB 2.75-2.85GHz 280W production ready
EPYK 9334 32/64 128MB 2.3-2.5GHz 210W production ready
EPYC 9274F 24/48 256MB 3.4-3.6GHz 320W production ready
EPYK 9254 24/48 128MB 2.4-2.5GHz 200W production ready
EPYK 9224 24/48 64MB 2.15-2.25GHz 200W production ready
EPYC 9174F 16/32 256MB 3.6-3.8GHz 320W production ready
EPYK 9124 16/32 64MB 2.6-2.7GHz 200W production ready
EPYC 9000 (ES) 96/192 384MB 2.0-2.15GHz 320-400W IT
EPYC 9000 (ES) 84/168 384MB 2.0GHz 290W IT
EPYC 9000 (ES) 64/128 256MB 2.5-2.65GHz 320-400W IT
EPYC 9000 (ES) 48/96 256MB 3.2-3.4GHz 360W IT
EPYC 9000 (ES) 32/64 256MB 3.2-3.4GHz 320W IT
EPYC 9000 (ES) 32/64 256MB 2.7-2.85GHz 260W IT

That being said, AMD’s EPYC Genoa CPUs are stated to have 128 PCIe Gen 5.0 lanes, 160 for a 2P (dual-socket) configuration. The SP5 platform will also offer DDR5-5200 memory support, which is a crazy improvement over the existing DDR4-3200MHz DIMMs. But that’s not all, it also supports up to 12 DDR5 memory channels and 2 DIMMs per channel, allowing up to 3TB of system memory with 128GB modules. The AMD EPYC 9000 Genoa CPU series is expected to be released in the second half of this year.

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